New M.E. Thesis Submitted from ECE Student

SRAM CELL DESIGN FOR LOW POWER CONSUMPTION By Ravinder Singh,Electronics

Abstract
Static Random Access Memory (SRAM) is low power consumption, volatile memory which finds its wide applications in advanced microprocessors and embedded systems. The Dynamic Random Access Memory (DRAM) is small in size but it has however not been used due to the specialized process steps needed, and associated high cost. Planar DRAMs using a standard Complementary Metal Oxide Semiconductor (CMOS) process, on the other hand, has not been proven to be viable for high-yield, high-volume production. This, together with the high performance demands of microprocessors, has resulted in the conventional six-transistor (6T) SRAMs being the main choice for today’s applications. In present work, a new approach to a fully static SRAM is used to replace the standard 6T SRAM cell. A low power 7T SRAM cell has been developed. The cell design works in its whole, but does not fully automatically deliver a complete circuit. Transistor sizing offers a great tool to trade off delay and energy. The key to low power operation in the SRAM data path is to reduce the signal swings in the high capacitance nodes like the bitlines and the data lines. By using the proposed small-swing bitline scheme, 74-77% of power in write cycles is saved. There is tradeoff among area, delay, and noise margin, which are governed by two design parameters,b and N , associated with the switch Vss. Decreasing b saves layout area but degrades both noise margin and read delay. The proposed scheme avoids the requirement of half- precharging of bitlines and negative voltage on cell source lines, which results in more write power saving without degrading cell stability and device reliability.


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